Field of the Invention
The present invention relates to electronic fuses (e-fuses). More specifically, the present invention relates to stacked via structures for metal fuse applications.
Description of the Related Art
In advanced technologies, e-fuses have been implemented at the polycrystalline silicon (PC) level. During programming, a high current pulse of short duration is passed through the structure. This irreversibly migrates silicide on top of the PC, causing a change in resistance and thus acting as a programmable fuse.
As scaling progresses, it is becoming harder to implement these e-fuses at the PC level due to drop in maximum allowable currents through the first metal layer or conductor. Also, the collateral damage associated with the event is becoming more difficult to contain. As a result, there is a drive to implement these fuses at the metal interconnect levels and use the phenomenon of electromigration (EM) to program the fuses.
The power requirements to cause EM in copper (Cu) interconnects are much larger than the typical PC level fuses. This is partly due to the fact that the liner materials used in Cu interconnects, such as tantalum (Ta) and tantalum nitride (TaN), must be blown along with the Cu in order to achieve proper fuse programming. Hence, there is a need to devise fuse structures that are susceptible to EM without compromising the reliability of the remaining interconnects.
In a conventional metal fuse approach, as shown in FIG. 1, a two-level structure comprises conductor 11 embedded in dielectric layer 10, and via 21 and line 22 embedded in dielectric layer 20. A cap layer 23 is typically deposited over line 22 and dielectric layer 20. Electron flow is from via 21 into line 22. A high current is applied between the positive current connection (I+) and negative current connection (I−) to induce EM failure. Voltage across the structure is measured using the positive (V+) and negative (V−) voltage connections. The electron flow through the fuse structure is from the lower level metal, conductor 11, to the upper level metal, line 22.
With this design, some of the failures occur in via 21 while other failures occur in line 22, resulting in a lack of control over the failure location and leading to variability in the final resistance of the fuse structure after programming. Moreover, it is not possible to electrically determine whether the failure is in via 21 or line 22. Failures in line 22 are less desirable because cap layer 23 may be compromised during the programming process.
The programming process with this design may lead to damage in the surrounding dielectric layer 20. It is likely that material from the blown fuse area will be present in the damaged dielectric region. If this is the case, then there is concern that the material will migrate throughout the dielectric, causing a short circuit to neighboring lines.
Therefore, a structure is needed such that failures occur preferentially in the via and not the line. Also, a detection method is needed to determine whether the programming process causes damage in the via or the line. The structure should allow for determining whether material from the blown fuse area has migrated into the dielectric region. It would also be desirable to prevent further migration of the blown fuse material.